RS、JK、D、T和T’触发器的逻辑功能及使用方法
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library ieee;
use ieee.std_logic_11.all;
entity jkdff is
port(pset,clr,clk,j,k:in std_logic;
q,qb:out std_logic);
end entity jkdff;
architecture rtl of jkdff is
signal q_s,qb_s:std_logic;
begin
process(pset,clr,clk,j,k)is
begin
if(pset='0')then
q_s<='1';
qb_s<='0';
elsif(clk 'event and clk='1')then
if(j='0')and(k='1')then
q_s<='0';
qb_s<='1';
elsif(j='1')and(k='0')then
q_s<='1';
qb_s<='0';
elsif(j='1')and(k='1')then
q_s<=not q_s;
qb_s<=not qb_s;
end if;
end if;
q<=q_s;
qb<=qb_s;
end process;
end architecture rtl;
